The biggest challenge in the IC design industry

The design industry in mainland China has begun to advance to the 65nm process, and the scale is also expanding. The requirements for EDA tools also have “Chinese characteristics”. Andrew Moore, Mentor Graphics Asia-Pacific Technical Director, said at the ICCAD2010 conference: “The requirements of the Chinese design industry for EDA tools are: First, the large-scale use of CPU cores such as ARM and MIPS in SoC design requires Co-design and verification of hardware and software requires hardware emulation accelerators, and physical verification tools, which were previously verified after placement and routing, and now it is time to place and route and verify simultaneously. It occupies most of the cost of the development process, and therefore it needs to speed up software development and reduce software development costs."

At the same time, although the IC design industry in mainland China continues to explore new heights, it still faces a number of invisible "barriers." "The challenge for China's IC design industry is that there are not many IP suppliers, which has caused Chinese domestic IC designers to find no suitable IP during design, or they need to spend more time integrating. The main reason is that the size of China's semiconductor industry is not yet Very big, some IP companies have not yet entered the Chinese market,” said Andrew Moore. However, he added that as China’s semiconductor industry continues to expand, some small and medium-sized IP companies will also enter the Chinese market, and this will not last long.

The problem of solving the cost and speed of software development has become a common "door of life" for EDA vendors. Therefore, Mentor’s strategy is to “bet” ESA. Andrew Moore made an image metaphor: "As in the PC industry, Windows provides a better platform than the previous DOS system. It is easy to develop software on this platform. ESA can also provide more in IC design. High-level platforms. EDA tools mainly assist in the design of hardware, while embedded software is implemented in hardware, which requires ESA support. Both can jointly serve the SoC design platform."

In addition, IC design continues to move toward SoC, involving the integration of IP from different sources. How can EDA vendors “think of people”? “EDA vendors can solve the problem of IP integration from different sources from four aspects: the first to do system-level design (ESL), the second to improve the efficiency of functional verification, and the third to achieve software and hardware co-design. The fourth is to cooperate with the foundry for DDM.” Peng Qihuang, president of Mentor Graphics Asia Pacific, pointed out that “For EDA suppliers, we must have good solutions in these four areas to help IC design company solves the design problem of large-scale SoC."

At the same time, low-power design has become an important part of IC design, and the problem of power consumption is already prominent at the 65nm node, and will be even more severe at the 40nm and 28nm nodes. "This requires solving the power consumption problem from two aspects of EDA verification and place and route, and to achieve this goal, the most important thing is to establish standards." Peng Qihuang said.

As the process continues to "fit" with Moore's Law, EDA suppliers need to be "right and left" in both mature and advanced processes, and Fabless, EDA, and Foundry need to work closely together.