According to an EETimes report on July 23, ARM and TSMC announced that they signed a long-term cooperation agreement. The two companies will use ARMv8 microprocessors as R&D targets to explore ways to use FinFET process technology to develop ARMv8's production process. According to the agreement, the technical fields of cooperation between the two companies will cover 20nm process technology nodes. According to reports, TSMC will achieve mass production of 20nm technology nodes by the end of 2013, and will implement 16nm process volume production in the new production line in 2015.
The FinFET process is moving toward mass-production cooperation between TSMC and ARM for FinFET process optimization, demonstrating that it has transitioned to the mass production phase of the FinFET process.
chip
ARMv8 is ARM's first 64-bit IP core. Before ARM provided users with IP cores that were designed using the mature technology of planar CMOS, it seems that there is no need to pay much attention to the production process. The process is simulated and passed on to the chip manufacturer for production. However, the technology below 20nm needs to be explored. The process parameters of the chip design software in the computer need to be verified with repeated verification between the manufacturer's process production line. In this exploration process, both the chip design manufacturer and the manufacturer are required. The close cooperation and repeated verification ensure that the computer simulation results of the design software are consistent with the new process on the chip production line, so as to ensure the yield requirement during the film production. The cooperation between the two companies this time is an inevitable choice based on their own development needs.
With Intel's recent announcement of the "TriGate architecture" 3D transistor process to successfully produce the smallest line width 22nm IvyBridge processor, began mass supply to the market, proving that the use of 3D transistor technology can significantly improve the performance of the chip, After reducing chip power consumption, the world's major semiconductor companies have now locked the next step in the development of stereoscopic semiconductor manufacturing processes. The FinFET process is currently one of the technical approaches that most companies intend to adopt. Another process that can achieve linewidths below 14nm is the FDSOI transistor technology. This is a homeopathic extension based on the current flat CMOS chip manufacturing process. IBM, Globalfoundries, TSMC, UMC and other companies are also working Study this process technology. According to reports, in addition to the above two approaches, a company called Suvolta joined forces with Fujitsu to introduce a third transistor technology solution.
Taiwan Semiconductor Manufacturing Co., Ltd. on the one hand stated that it joined the IBM and other camps at 20nm node to cooperate in the research and development of planar process technology for FDSOI. On the other hand, in the past few years, it has vigorously carried out R&D of FinFET three-dimensional structure process technology, and this time it has cooperated with ARM on FinFET process optimization. It shows that it has completed a single R&D of the FinFET process and began the transition to mass production of the FinFET process. With the ARMv8 core as the object, process optimization at the mass production stage was performed to achieve perfection.
Two technologies will coexist
Both FinFET and UTB-SOI will be useful. Unless UTB-SOI performs well, FinFET technology will not be defeated.
What is the difference between TSMC's FinFET process and Intel's recently announced three-gate 3D transistor process? Will there be any entanglement of intellectual property rights between them? What impact will there be on the further development of the semiconductor manufacturing process in the future? According to the relevant information, in fact, the FinFET process announced by many companies, including Samsung and others, is essentially a matter once again in terms of theory and model. However, each one is exploring and the specific details of the implementation will be different. For business confidentiality needs, it is estimated that each will not publish their own "trick" and details.
According to relevant data reports, two types of 14nm manufacturing process FinFET and FDSOI transistor technologies are currently being explored in the industry. The source of these technical solutions comes from a semiconductor technology research result by Professor Hu Zhengming from Taiwan in 1999. The results of this study show that there are two ways to achieve the 25nm process goals: one is a three-dimensional structure of FinFET transistors, and the other is based on SOI ultra-thin insulating layer silicon technology (UTB-SOI, which is what we often say FDSOI Transistor technology).
At the time, the research concluded that it would be difficult to produce a very thin silicon film on UTB-SOI. To make UTB-SOI work properly, the thickness of the silicon film on the insulating layer should be limited to about 1/4 of the gate length. For a transistor with a 25-nm gate length, Professor Hu believes that the thickness of the UTB-SOI silicon film should be controlled at around 5 nm, which was considered impossible at that time.
However, when Soitec of France began launching wafer samples of 300mm UTB-SOI in 2009, the original thickness of the silicon film on the top layer of these wafers was only 12nm, and then processed to remove the top 7nm silicon film, resulting in a thickness of 5nm. After silicon film, this paved the way for the practical application of UTB-SOI technology. UTB-SOI seems to have more advantages in R&D complexity because UTB-SOI can still be implemented using current conventional planar transistor process technology, while FinFET is a three-dimensional transistor technology, and more aspects will need to be changed.
Professor Hu believes that UTB-SOI will have a market in the future, because the complexity of this technology is lower than that of FinFET, and chip manufacturing companies only need to buy UTB-SOI wafers. UTB-SOI technology will be an attractive option for low-power applications with low frequency requirements. FinFET and UTB-SOI technologies can coexist. Intel's use of FinFET technology is due to the fact that this technology can make the performance of the microprocessor relatively stronger. TSMC will first adopt FinFET technology. After all, they have spent a lot of years of research and development investment in this area, and TSMC has accumulated a large number of high-performance applications for FinFET applications.
TSMC will start using FinFET technology at the 14nm node and will also introduce process technology services using UTB-SOI technology for users of low-power products. UMC will reduce its investment in FinFET technology and move directly to UTB-SOI technology. At present, it has signed a UTB-SOI technology licensing agreement with IBM and intends to go down UTB-SOI technology.
At present, most people in the industry believe that for the next generation of semiconductor chip products, FinFET and UTB-SOI will have their own use. However, unless UTB-SOI can achieve higher performance, it will not be able to defeat FinFET technology. For many chip manufacturing companies, many applications for UTB-SOI technology can still be found. Therefore, both technologies are likely to realize and have their own markets, and in the very long time in the future, the two technologies will coexist for a long time, giving chip designers an alternative.
The FinFET process is moving toward mass-production cooperation between TSMC and ARM for FinFET process optimization, demonstrating that it has transitioned to the mass production phase of the FinFET process.
chip
ARMv8 is ARM's first 64-bit IP core. Before ARM provided users with IP cores that were designed using the mature technology of planar CMOS, it seems that there is no need to pay much attention to the production process. The process is simulated and passed on to the chip manufacturer for production. However, the technology below 20nm needs to be explored. The process parameters of the chip design software in the computer need to be verified with repeated verification between the manufacturer's process production line. In this exploration process, both the chip design manufacturer and the manufacturer are required. The close cooperation and repeated verification ensure that the computer simulation results of the design software are consistent with the new process on the chip production line, so as to ensure the yield requirement during the film production. The cooperation between the two companies this time is an inevitable choice based on their own development needs.
With Intel's recent announcement of the "TriGate architecture" 3D transistor process to successfully produce the smallest line width 22nm IvyBridge processor, began mass supply to the market, proving that the use of 3D transistor technology can significantly improve the performance of the chip, After reducing chip power consumption, the world's major semiconductor companies have now locked the next step in the development of stereoscopic semiconductor manufacturing processes. The FinFET process is currently one of the technical approaches that most companies intend to adopt. Another process that can achieve linewidths below 14nm is the FDSOI transistor technology. This is a homeopathic extension based on the current flat CMOS chip manufacturing process. IBM, Globalfoundries, TSMC, UMC and other companies are also working Study this process technology. According to reports, in addition to the above two approaches, a company called Suvolta joined forces with Fujitsu to introduce a third transistor technology solution.
Taiwan Semiconductor Manufacturing Co., Ltd. on the one hand stated that it joined the IBM and other camps at 20nm node to cooperate in the research and development of planar process technology for FDSOI. On the other hand, in the past few years, it has vigorously carried out R&D of FinFET three-dimensional structure process technology, and this time it has cooperated with ARM on FinFET process optimization. It shows that it has completed a single R&D of the FinFET process and began the transition to mass production of the FinFET process. With the ARMv8 core as the object, process optimization at the mass production stage was performed to achieve perfection.
Two technologies will coexist
Both FinFET and UTB-SOI will be useful. Unless UTB-SOI performs well, FinFET technology will not be defeated.
What is the difference between TSMC's FinFET process and Intel's recently announced three-gate 3D transistor process? Will there be any entanglement of intellectual property rights between them? What impact will there be on the further development of the semiconductor manufacturing process in the future? According to the relevant information, in fact, the FinFET process announced by many companies, including Samsung and others, is essentially a matter once again in terms of theory and model. However, each one is exploring and the specific details of the implementation will be different. For business confidentiality needs, it is estimated that each will not publish their own "trick" and details.
According to relevant data reports, two types of 14nm manufacturing process FinFET and FDSOI transistor technologies are currently being explored in the industry. The source of these technical solutions comes from a semiconductor technology research result by Professor Hu Zhengming from Taiwan in 1999. The results of this study show that there are two ways to achieve the 25nm process goals: one is a three-dimensional structure of FinFET transistors, and the other is based on SOI ultra-thin insulating layer silicon technology (UTB-SOI, which is what we often say FDSOI Transistor technology).
At the time, the research concluded that it would be difficult to produce a very thin silicon film on UTB-SOI. To make UTB-SOI work properly, the thickness of the silicon film on the insulating layer should be limited to about 1/4 of the gate length. For a transistor with a 25-nm gate length, Professor Hu believes that the thickness of the UTB-SOI silicon film should be controlled at around 5 nm, which was considered impossible at that time.
However, when Soitec of France began launching wafer samples of 300mm UTB-SOI in 2009, the original thickness of the silicon film on the top layer of these wafers was only 12nm, and then processed to remove the top 7nm silicon film, resulting in a thickness of 5nm. After silicon film, this paved the way for the practical application of UTB-SOI technology. UTB-SOI seems to have more advantages in R&D complexity because UTB-SOI can still be implemented using current conventional planar transistor process technology, while FinFET is a three-dimensional transistor technology, and more aspects will need to be changed.
Professor Hu believes that UTB-SOI will have a market in the future, because the complexity of this technology is lower than that of FinFET, and chip manufacturing companies only need to buy UTB-SOI wafers. UTB-SOI technology will be an attractive option for low-power applications with low frequency requirements. FinFET and UTB-SOI technologies can coexist. Intel's use of FinFET technology is due to the fact that this technology can make the performance of the microprocessor relatively stronger. TSMC will first adopt FinFET technology. After all, they have spent a lot of years of research and development investment in this area, and TSMC has accumulated a large number of high-performance applications for FinFET applications.
TSMC will start using FinFET technology at the 14nm node and will also introduce process technology services using UTB-SOI technology for users of low-power products. UMC will reduce its investment in FinFET technology and move directly to UTB-SOI technology. At present, it has signed a UTB-SOI technology licensing agreement with IBM and intends to go down UTB-SOI technology.
At present, most people in the industry believe that for the next generation of semiconductor chip products, FinFET and UTB-SOI will have their own use. However, unless UTB-SOI can achieve higher performance, it will not be able to defeat FinFET technology. For many chip manufacturing companies, many applications for UTB-SOI technology can still be found. Therefore, both technologies are likely to realize and have their own markets, and in the very long time in the future, the two technologies will coexist for a long time, giving chip designers an alternative.
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