The normal use of a D flip-flop is typically used as a divide-by-2, counter or shift register. However, as long as the peripheral circuit of the D flip-flop is improved, according to its basic logic function. It can make full use of its unique role. A pulse width detecting circuit commonly used in digital devices recognizes the width of a pulse signal, for example, when the width of the input pulse is a specific value. A response is generated, otherwise it will not respond. The following is a description of several pulse width detection circuits composed of CMOS dual D flip-flop CD4013.
One of the detection lines is shown in Figure 1. ICl and IC2 are a CD4013, in which ICl constitutes a monostable flip-flop, the monostable output terminal Q1 acts as the clock pulse of the D flip-flop IC2, and the Q2 terminal acts as the vo output terminal. Since the set S terminal of ICl and IC2 is grounded, the Q1 terminal of ICl is always zero at steady state, the Q1 terminal is at a high level, and the VO output is at a low level. When the Vi input signal is high, the high level of the D1 terminal is sent to the ICl flip-flop, the Q1 terminal jumps to the high level, the Ql terminal is the low level, the temporary steady state starts, the IC2 flip-flop does not trigger, the VO still Is low. When Vi is down, the transient state of the ICl monostable circuit has not ended (see Figure 2b), the IC2 flip-flop has not yet triggered, and VO is low. After the temporary steady state of ICl is over, the ICI flip-flop is reset, the Q1 terminal is low level, and the Q1 terminal is high. Despite the CL on the CL2 end of IC2. However, since the Vi input signal is already at a low level, the inverter R is inverted by the inverter F to make the reset terminal R2 of the IC2 high, so the VO terminal is still at a low level.
Another case is: When Vi is high and Ql is low, ICl temporarily starts and VO is low. When the temporary steady state of ICl is over, Vi is still high (as shown in Figure 2a), Q1 jumps up, IC2 triggers flip, R2 is low, and D2 is sent to IC2, VO The output is high. When Vi jumps, F2 causes IC2's R2 terminal to be high, forcing IC2 to reset. The VO output is low.
It can be seen that only when the Vi input signal pulse width is large and the monostable output pulse width of the IC1 is dry. The IC2 trigger has an output.
The second test line is shown in Figure 3. This line is similar to Figure 1, except that the Vi input signal is inverted by inverter F and acts as the CL2 clock pulse for IC2. ICl is still a one-shot circuit. At steady state, V0 is low. When Vi is high, the Q1 terminal is high, the temporary steady state starts, IC2 is not triggered, and V0 is low. When the monolithic end of ICl is over (see Figure 4b), the Ql terminal returns to a low level, and Vi is still at a high level, so VO is low. When Vi jumps, it is inverted by F. The LC2 terminal of IC2 jumps, but since the Q1 terminal, that is, the R2 terminal of ZC2 is at a high level, VO is still at a low level.
Another case is: When Vi is high, Ql is high, ICl is temporarily turned on, IC2 is not triggered, and V0 is low. When Vi squats, the transient steady state is not over, Q1 is still low, IC2 triggers flipping, and VO outputs high (see Figure 4a). When the ICl monostable circuit is temporarily terminated, the Q1 terminal jumps to a high level, forcing IC2 to reset and the VO output to be low. It can be seen that only when the pulse width of the Vi input signal is smaller than the monostable output pulse width of ICl. The IC2 trigger has an output.
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